Various communication protocols such as IEEE 802.3, also known as Ethernet, use multiple lanes of serial data to increase the bandwidth of communication links. These links may use electrical signaling for the entire path, or combination of electrical and optical signaling for different parts of the path. Most of the high speed protocols use an embedded clock in the data stream. Clock and data recovery (CDR) circuits are used to recover the data at the destination. As the data rate of each lane increases, signal integrity is an issue that becomes more challenging. Some of the solutions to signal integrity are transmitter and receiver equalization, performing clock and data recovery at points along the data channel, and crosstalk cancellation. Some protocols such as Ethernet 10G BaseT inherently have all of the lanes operating with the same clock frequency, and can require sharing of transmitted and received data between channels for the purpose of crosstalk cancellation. In multi-channel CDR circuits opportunities exist to improve the ability of the channels to adapt to the data characteristics.